1. Field of the Invention
The invention relates generally to the vertical semiconductor power devices. More particularly, this invention relates to configurations and methods of manufacturing of vertical semiconductor power devices with transistor cells with non-uniform ballasted sources to protect the semiconductor power devices to reliably operate at high power and high temperature conditions.
2. Description of the Prior Art
Conventional technologies of manufacturing and configuring semiconductor power devices are still confronted with a technical difficulty that devices provided for reliably operating at high power and high temperature usually have high Rdson resistance. Specifically, high reliability is expected from power transistors designed for operating at high power, i.e., high voltage and current, and high temperature applications. One exemplary application is the power transistors implemented in the DC brushless motor control. On the one hand the reliability of the power transistors, such as a MOSFET device, is improved because of the positive temperature coefficient of the Rdson resistance. But in the meantime, the threshold voltage of a MOSFET device has a negative temperature coefficient at relatively low currents and in the linear mode of operation. The leads to a condition that the net voltage (Vgs−Vt), i.e., the gate to drain voltage Vgs minus the threshold voltage Vt, can increase with increasing temperature. A temperature runaway condition may occur to cause a device failure. The temperature runaway problem may occur to both the trench-gate DMOS devices as well as planar power MOSFET devices due to the underlined phenomenon of the negative temperature coefficient of the threshold voltage.
In order to overcome such difficulties, a technique of source ballasting is implemented to improve the thermal stability of the MOSFET devices. The source ballasting technique is similar to the emitter ballasting applied in the bipolar technology. FIG. 1 depicts a MOSFET device implementing a source-ballasting configuration. The MOSFET device includes a source region encompassed inside a body region wherein a portion of the source region shown as S-ballast is doped with a lower concentration of source dopant. The S-ballast region constitutes a ballast resistor Rs for providing a feedback to counter the increase of the voltage due to the negative temperature coefficient of the threshold voltage. The source to drain current, i.e., Ids, increases due to the increase of the voltage when the threshold voltage is reduced with increased temperature. The Rdson thus increases to limit further increase of the current for preventing a thermal runaway problem. Significant increase of Rdson resistance often adversely affects the device performance due to a conventional configuration of uniformly implementing the source ballasting over the entire areas of the semiconductor power devices.
Specifically, the source ballasting techniques have been disclosed in U.S. Pat. Nos. 5,475,252, 5,763,9191, 6,268,286, 6,331,726, 6,441,410, 6,583,972, 6,587,320, and 6,927,458. The semiconductor power devices such as MOSFET devices disclosed in these patented inventions implement a technique of uniform ballasting to increase the thermal stability. However, the Rdson is greatly increased and the device performance is adversely affected due the uniform addition of the source resistance by implementing the conventional ballasting technologies.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new device configurations and methods of manufacturing the power devices such that the above discussed problems and limitations can be resolved.